1. Field of the Invention
The present invention relates to a switching regulator, and particularly to a synchronous rectification switching regulator.
2. Description of Related Art
Power supply voltage to be applied to a semiconductor device has been decreasing with the reduction in size of semiconductor devices. To supply power to such semiconductor devices, synchronous rectification switching regulators are often used. A switching regulator steps down or steps up voltage from a power supply, such as a battery, to apply the resultant voltage, as power, to a semiconductor device. When the load current decreases in such a switching regulator under light load conditions, the direction of the current flowing through an output inductor is inverted, so that the current flows from the output inductor to ground through a synchronous rectifier transistor, in some cases. Since the current is supplied from an output capacitor without being supplied to the load, the power is wasted. To solve this, Patent documents 1, 2 and 3 each disclose a technique to detect an inversion of the direction of current flowing through an inductor under light load conditions, and to perform, upon detection, control such that a synchronous rectifier transistor can be turned off.
For example, the DC-DC converter described in Patent document 1 includes: a first potential; a pair of power transistors, which are disposed in series between the first potential and a second potential, the second potential being lower than the first potential, and which convert direct current voltage of the potential difference between the first and second potentials into alternating current voltage; detection means, which outputs a detection signal when the alternating current voltage is lower than the second potential by a predetermined value; and a control circuit, which is provided for controlling the pair of power transistors, and which turns off the power transistor (a synchronous rectifier transistor) disposed on the second potential side, in response to the detection signal.
In the above DC-DC converter, the detection means outputs a detection signal when the alternating current voltage is lower than the second potential by the predetermined value. Thus, a detection signal is outputted before the alternating current voltage becomes equal to the second potential. This makes it possible to compensate for the effect of delay time caused by the detection means, thereby to highly accurately turn off the power transistor (a synchronous rectifier transistor) around an operation range in which the alternating current becomes 0.
[Patent document 1] Japanese Patent Laid Open Application No. 2006-333689
[Patent document 2] Japanese Patent Laid Open Application No. 2007-20315
[Patent document 3] Japanese Patent Laid Open Application No. 2007-6555
As the above detection means, a comparator is generally used. A comparator compares the voltages of a non-inverting (+) input terminal and an inverting (−) input terminal, and sets an output (OUT) at high level when the voltage of the + input terminal (CP+) is higher than the voltage of the − input terminal (CP−) while setting an output (OUT) at low level when the voltage of the + input terminal (CP+) is lower than the voltage of the − input terminal (CP−).
FIG. 8 is charts schematically showing operation waveforms of the comparator. As shown in FIG. 8 (A), when the voltage of the + input terminal (CP+) decreases to a voltage lower than the voltage of the − input terminal (CP−), the output (OUT) is switched from high level to low level with a delay of a time period Td1. By contrast, when the voltage (CP+) increases to a voltage higher than the voltage (CP−), the output (OUT) is switched from low level to high level with a delay of a time period Td2.
Assume that the voltage (CP+) decreases to a voltage lower than the voltage (CP−) by ΔV. When ΔV is small, the time periods Td1 and Td2 increase as shown in FIG. 8 (B), in other words, reaction of comparison operation is slower. Moreover, when ΔV is even smaller, the output (OUT) is kept at high level without being switched to low level, as shown in FIG. 8 (C). Thus, the comparator has characteristics of not outputting any comparison result of comparison operation in a case where a difference between levels of input comparison signals is extremely small and where the duration time of such condition is shorter than a time duration called dead zone width.
When load current decreases under light load conditions, the above-mentioned alternating current voltage becomes slightly lower than the second potential by a predetermined value. In this case, there is a possibility that the comparator does not output any comparison result because of the above-described characteristics of the comparator, so that the synchronous rectifier transistor is not turned off. Accordingly, the comparator cannot carry out comparison operation with high accuracy under light load conditions and hence the synchronous rectifier transistor is not turned off. This may possibly reduce efficiency in power conversion under light load conditions.